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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

VLDM{}{.} {!}, <br />

where:<br />

The addressing mode:<br />

Instruction Details<br />

IA Increment After. The consecutive addresses start at the address specified in .<br />

This is the default <strong>and</strong> can be omitted. Encoded as P = 0, U = 1.<br />

DB Decrement Before. The consecutive addresses end just before the address<br />

specified in . Encoded as P = 1, U = 0.<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the<br />

registers in .<br />

The base register. The SP can be used. In the <strong>ARM</strong> instruction set, if ! is not specified the<br />

PC can be used.<br />

! Causes the instruction to write a modified value back to . This is required if<br />

== DB, <strong>and</strong> is optional if == IA. Encoded as W = 1.<br />

If ! is omitted, the instruction does not change in this way. Encoded as W = 0.<br />

The extension registers to be loaded, as a list of consecutively numbered doubleword<br />

(encoding T1 / A1) or singleword (encoding T2 / A2) registers, separated by commas <strong>and</strong><br />

surrounded by brackets. It is encoded in the instruction by setting D <strong>and</strong> Vd to specify the<br />

first register in the list, <strong>and</strong> imm8 to twice the number of registers in the list (encoding<br />

T1 / A1) or the number of registers in the list (encoding T2 / A2). must contain at<br />

least one register. If it contains doubleword registers it must not contain more than 16<br />

registers.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);<br />

address = if add then R[n] else R[n]-imm32;<br />

if wback then R[n] = if add then R[n}+imm32 else R[n]-imm32;<br />

for r = 0 to regs-1<br />

if single_regs then<br />

S[d+r] = MemA[address,4]; address = address+4;<br />

else<br />

word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;<br />

// Combine the word-aligned words in the correct order for current endianness.<br />

D[d+r] = if BigEndian() then word1:word2 else word2:word1;<br />

Exceptions<br />

Undefined Instruction, Data Abort.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-627

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