ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The translate and lock model
ARMv4 and ARMv5 Differences
This mechanism uses explicit TLB operations to translate and lock specific addresses into the TLB. Entries
are unlocked on a global basis using the unlock operations. Addresses are loaded using their MVA. The
following actions are UNPREDICTABLE:
accessing these functions with read (MRC) commands
using functions when the MMU is disabled
trying to translate and lock an address that is already present in the TLB.
Any abort generated during the translation is reported as a lock abort in the FSR. Only external aborts and
Translation faults are guaranteed to be detected. Any access permission, domain, or alignment checks on
these functions are IMPLEMENTATION DEFINED. Operations that generate an abort do not affect the target
TLB.
Where this model is applied to a unified TLB, the data TLB operations must be used.
Invalidate_all (I,D, or I and D) operations have no effect on locked entries.
TLB lockdown procedure, using the translate and lock model
All previously locked entries can be unlocked by issuing the appropriate unlock operation, I or D side.
Explicit lockdown operations are then issued with the required MVA in register Rt.
TLB unlock procedure, using the translate and lock model
Issuing the appropriate unlock (I or D) TLB operation unlocks all locked entries. It is IMPLEMENTATION
DEFINED whether an invalidate by MVA TLB operation removes the lock condition.
Note
The invalidate behavior is different in the TLB locking by entry model, where the invalidate by MVA
operation is guaranteed to occur.
H.7.14 c13, VMSA FCSE support
The FCSE described in Appendix E Fast Context Switch Extension (FCSE) is an IMPLEMENTATION DEFINED
option in ARMv4 and ARMv5. The feature is supported by the FCSEIDR as described in c13, FCSE
Process ID Register (FCSEIDR) on page B3-152. The Context ID and Software Thread ID registers listed
for ARMv7 are not supported in ARMv4 and ARMv5.
H.7.15 c15, IMPLEMENTATION DEFINED
CP15 c15 is reserved for IMPLEMENTATION DEFINED use. It is typically used for processor-specific runtime
and test features.
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