ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Architecture, bits [19:16]
Table B4-11 shows the permitted values for this field:
All other values are reserved by ARM and must not be used.
Primary part number, bits [15:4]
Revision, bits [3:0]
Protected Memory System Architecture (PMSA)
An IMPLEMENTATION DEFINED primary part number for the device.
Note
On processors implemented by ARM, if the top four bits of the primary part number are 0x0
or 0x7, the variant and architecture are encoded differently, see c0, Main ID Register (MIDR)
on page AppxH-34. Processors implemented by ARM have an Implementer code of 0x41.
An IMPLEMENTATION DEFINED revision number for the device.
ARMv7 requires all implementations to use the CPUID scheme, described in Chapter B5 The CPUID
Identification Scheme, and an implementation is described by the MIDR and the CPUID registers.
Note
For an ARMv7 implementation by ARM, the MIDR is interpreted as:
Bits [31:24] Implementer code, must be 0x41.
Bits [23:20] Major revision number, rX.
Bits [19:16] Architecture code, must be 0xF.
Bits [15:4] ARM part number.
Bits [3:0] Minor revision number, pY.
Table B4-11 Architecture codes
Bits [19:16] Architecture
0x1 ARMv4
0x2 ARMv4T
0x3 ARMv5 (obsolete)
0x4 ARMv5T
0x5 ARMv5TE
0x6 ARMv5TEJ
0x7 ARMv6
0xF Defined by CPUID scheme
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-33