ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.396 VST3 (single 3-element structure from one lane)
This instruction stores one 3-element structure to memory from corresponding elements of three registers.
For details of the addressing mode see Advanced SIMD addressing mode on page A7-30.
Encoding T1 / A1 Advanced SIMD
VST3. , []{!}
VST3. , [],
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 D 0 0 Rn Vd size 1 0 index_align Rm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 1 0 index_align Rm
if size == ‘11’ then UNDEFINED;
case size of
when ‘00’
if index_align != ‘0’ then UNDEFINED;
ebytes = 1; esize = 8; index = UInt(index_align); inc = 1;
when ‘01’
if index_align != ‘0’ then UNDEFINED;
ebytes = 2; esize = 16; index = UInt(index_align);
inc = if index_align == ‘0’ then 1 else 2;
when ‘10’
if index_align != ‘00’ then UNDEFINED;
ebytes = 4; esize = 32; index = UInt(index_align);
inc = if index_align == ‘0’ then 1 else 2;
d = UInt(D:Vd); d2 = d + inc; d3 = d2 + inc; n = UInt(Rn); m = UInt(Rm);
wback = (m != 15); register_index = (m != 15 && m != 13);
if d3 > 31 then UNPREDICTABLE;
Assembler syntax
VST3. , [] Rm = ’1111’
VST3. , []! Rm = ’1101’
VST3. , [], Rm = other values
where:
See Standard assembler syntax fields on page A8-7. An ARM VST3 instruction must be
unconditional.
The data size. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
A8-778 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B