ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.2.6 Saturating addition and subtraction
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 op 0 0 1 0 1
Table A5-8 shows the allocation of encodings in this space. These encodings are all available in ARMv5TE
and above, and are UNDEFINED in earlier variants of the architecture.
A5.2.7 Halfword multiply and multiply-accumulate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 op1 0 1 op 0
Table A5-9 shows the allocation of encodings in this space.
Table A5-8 Saturating addition and subtraction instructions
op Instruction See
00 Saturating Add QADD on page A8-250
01 Saturating Subtract QSUB on page A8-264
10 Saturating Double and Add QDADD on page A8-258
11 Saturating Double and Subtract QDSUB on page A8-260
These encodings are signed multiply (SMUL) and signed multiply-accumulate (SMLA) instructions, operating
on 16-bit values, or mixed 16-bit and 32-bit values. The results and accumulators are 32-bit or 64-bit.
These encodings are all available in ARMv5TE and above, and are UNDEFINED in earlier variants of the
architecture.
op1 op Instruction See
Table A5-9 Halfword multiply and multiply-accumulate instructions
00 - Signed 16-bit multiply, 32-bit accumulate SMLABB, SMLABT, SMLATB, SMLATT on
page A8-330
01 0 Signed 16-bit x 32-bit multiply, 32-bit accumulate SMLAWB, SMLAWT on page A8-340
01 1 Signed 16-bit x 32-bit multiply, 32-bit result SMULWB, SMULWT on page A8-358
10 - Signed 16-bit multiply, 64-bit accumulate SMLALBB, SMLALBT, SMLALTB, SMLALTT
on page A8-336
11 - Signed 16-bit multiply, 32-bit result SMULBB, SMULBT, SMULTB, SMULTT on
page A8-354
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