ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The DCC status flags themselves:
— DBGDSCR.TXfull, bit [29]
— DBGDSCR.TXfull_l, bit [26]
— DBGDSCR.RXfull, bit [30]
— DBGDSCR.RXfull_l, bit [27].
Debug Register Interfaces
Note
Reading DBGDSCR through the DBGOSSRR has no side-effects, that is, the values of TXfull_l and
RXfull_l are unchanged.
All other writable flags in the DBGDSCR:
— Method of Debug Entry bits, MOE, bits [5:2]
— Force Debug Acknowledge bit, DBGack, bit [10]
— Interrupts Disable bit, INTdis, bit [11]
— User mode Access to Communication Channel Enable bit, UDCCdis, bit [12]
— Execute ARM Instruction Enable bit, ITRen, bit [13]
— Halting debug-mode Enable bit, HDBGen, bit [14]
— Monitor debug-mode Enable bit, MDBGen, bit [15]
— External DCC access mode field, ExtDCCmode, bits [21:20].
If vectored interrupt support is implemented and enabled, all state required to ensure the correct
generation of Vector Catch debug events. For more information, see Vector catch debug events and
vectored interrupt support on page C3-22.
The OS Save sequence must preserve at least all of this debug logic state that is lost when the core power
domain is powered down. The OS Save sequence does not have to preserve any debug logic state that is not
lost when the core power domain is powered down. That is, it does not have to preserve any debug logic
state that is in the debug power domain.
The OS Save and Restore mechanism does not preserve:
The sticky exception flags in the DBGDSCR, and the contents of the DBGITR.
The read-only processor status flags in the DBGDSCR:
— HALTED, bit [0]
— RESTARTED, bit [1]
— SPIDdis, bit [16]
— SPNIDdis, bit [17]
— NS, bit [18]
— ADAdiscard, bit [19]
— InstrCompl_l, bit [24]
— PipeAdv, bit [25].
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-11