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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

MUL{S} {,} , <br />

where:<br />

Instruction Details<br />

S If S is present, the instruction updates the flags. Otherwise, the flags are not updated.<br />

In the Thumb instruction set, S can be specified only if both <strong>and</strong> are R0-R7 <strong>and</strong><br />

the instruction is outside an IT block.<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

The destination register.<br />

The first oper<strong>and</strong> register.<br />

The second oper<strong>and</strong> register.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations();<br />

oper<strong>and</strong>1 = SInt(R[n]); // oper<strong>and</strong>1 = UInt(R[n]) produces the same final results<br />

oper<strong>and</strong>2 = SInt(R[m]); // oper<strong>and</strong>2 = UInt(R[m]) produces the same final results<br />

result = oper<strong>and</strong>1 * oper<strong>and</strong>2;<br />

R[d] = result;<br />

if setflags then<br />

APSR.N = result;<br />

APSR.Z = IsZeroBit(result);<br />

if ArchVersion() == 4 then<br />

APSR.C = bit UNKNOWN;<br />

// else APSR.C unchanged<br />

// APSR.V always unchanged<br />

Exceptions<br />

None.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-213

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