ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.278 VBIC (register)
Vector Bitwise Bit Clear (register) performs a bitwise AND between a register value and the complement
of a register value, and places the result in the destination register.
Encoding T1 / A1 Advanced SIMD
VBIC , ,
VBIC , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 1 0 D 0 1 Vn Vd 0 0 0 1 N Q M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 0 0 D 0 1 Vn Vd 0 0 0 1 N Q M 1 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == ‘0’ then 1 else 2;
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