ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The mapping between the registers is as follows:
S maps to the least significant half of D
S maps to the most significant half of D
D maps to the least significant half of Q
D maps to the most significant half of Q.
Application Level Programmers’ Model
For example, you can access the least significant half of the elements of a vector in Q6 by referring to D12,
and the most significant half of the elements by referring to D13.
Pseudocode details of Advanced SIMD and VFP extension registers
The pseudocode function VFPSmallRegisterBank() returns FALSE if all of the 32 registers D0-D31 can be
accessed, and TRUE if only the 16 registers D0-D15 can be accessed:
boolean VFPSmallRegisterBank()
In more detail, VFPSmallRegisterBank():
returns TRUE for a VFPv2 or VFPv3-D16 implementation
for a VFPv3-D32 implementation:
— returns FALSE if CPACR.D32DIS == 0
— returns TRUE if CPACR.D32DIS == 1 and CPACR.ASEDIS == 1
— results in UNPREDICTABLE behavior if CPACR.D32DIS == 1 and CPACR.ASEDIS == 0.
For details of the CPACR register, see:
c1, Coprocessor Access Control Register (CPACR) on page B3-104 for a VMSA implementation
c1, Coprocessor Access Control Register (CPACR) on page B4-51 for a PMSA implementation.
The S0-S31, D0-D31, and Q0-Q15 views of the registers are provided by the following functions:
// The 64-bit extension register bank for Advanced SIMD and VFP.
array bits(64) _D[0..31];
// S[] - non-assignment form
// =========================
bits(32) S[integer n]
assert n >= 0 && n = 0 && n