ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Access permissions for the external debug interface
Table C6-17 summarizes the access permissions for the external debug interface.
Debug Register Interfaces
OS Lock DBGOSLSR[1] = 1 Permissions in relation to locks on
page C6-27
Software Lock DBGLSR[1] = 1
Debug Software
Enable
Table C6-16 Meaning of (Argument = 1) for the control condition (continued)
Control condition Meaning of (Argument = 1) For details see
The recommended function of the DAP is
enabled
a. On a SinglePower system, the Processor powered control condition is equivalent to having both Debug logic powered
and Core logic powered on a system with the recommended separate debug and core power domains.
When the debug logic is not powered, external debug accesses must be prohibited. An implementation can
either ignore or abort these accesses.
Table C6-17 Register access permissions for the external debug interface a
Debug logic powered? b
No Not possible -
Yes Proceed Yes
Response Writes or has other side-effects?
a. See Meanings of terms and abbreviations used in this section on page C6-46 when
using this table.
b. Or Processor powered, on a SinglePower system.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-47