ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.2.4 Register specifiers
The , , and fields contain register specifiers, or in some cases scalar specifiers or register
lists. Table A7-4 shows the register and scalar specifier formats that appear in the instruction descriptions.
If is omitted, it is the same as .
Usual meaning a
Table A7-4 Advanced SIMD and VFP register specifier formats
A quadword destination register for the result vector (Advanced SIMD only).
A quadword source register for the first operand vector (Advanced SIMD only).
A quadword source register for the second operand vector (Advanced SIMD only).
A doubleword destination register for the result vector.
A doubleword source register for the first operand vector.
A doubleword source register for the second operand vector.
A singleword destination register for the result vector (VFP only).
A singleword source register for the first operand vector (VFP only).
A singleword source register for the second operand vector (VFP only).
A destination scalar for the result. Element x of vector . (Advanced SIMD only).
A source scalar for the first operand. Element x of vector . (Advanced SIMD only).
A source scalar for the second operand. Element x of vector . (Advanced SIMD only).
An ARM core register. Can be source or destination.
An ARM core register. Can be source or destination.
a. In some instructions the roles of registers are different.
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