ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.4.3 Two registers and a scalar
If B == 0b11, see Advanced SIMD data-processing instructions on page A7-10.
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 1 B A 1 0
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 B A 1 0
Table A7-11 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
Table A7-11 Data-processing instructions with two registers and a scalar
A U Instruction See
0x0x - Vector Multiply Accumulate or Subtract VMLA, VMLAL, VMLS, VMLSL (by scalar) on
page A8-638
0x10 - Vector Multiply Accumulate or Subtract Long VMLA, VMLAL, VMLS, VMLSL (by scalar) on
page A8-638
0x11 0 Vector Saturating Doubling Multiply
Accumulate or Subtract Long
VQDMLAL, VQDMLSL on page A8-702
100x - Vector Multiply VMUL, VMULL (by scalar) on page A8-666
1010 - Vector Multiply Long VMUL, VMULL (by scalar) on page A8-666
1011 0 Vector Saturating Doubling Multiply Long VQDMULL on page A8-706
1100 - Vector Saturating Doubling Multiply returning
High Half
1101 - Vector Saturating Rounding Doubling
Multiply returning High Half
VQDMULH on page A8-704
VQRDMULH on page A8-712
A7-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B