ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
If the processor cannot obtain the lock, it reads the lock value repeatedly in a tight loop until the lock
becomes available. At this point it again attempts to obtain the lock.
However, this spin-lock mechanism is not ideal for all situations:
in a low-power system the tight read loop is undesirable because it uses energy to no effect
in a multi-threaded processor the execution of spin-locks by waiting threads can significantly degrade
overall performance.
Therefore, ARMv7 provides an alternative locking mechanism based on events. The Wait For Event lock
mechanism permits a processor that has failed to obtain a lock to enter a low-power state. When the
processor that currently holds the required lock releases the lock it sends an event that causes any waiting
processors to wake up and attempt to gain the lock again.
Note
Although a complex operating system can contain thousands of distinct locks, the event sent by this
mechanism does not indicate which lock has been released. If the event relates to a different lock, or if
another processor acquires the lock more quickly, the processor fails to acquire the lock and can re-enter the
low-power state waiting for the next event.
The Wait For Event system relies on hardware and software working together to achieve energy saving:
the hardware provides the mechanism to enter the Wait For Event low-power state
the operating system software is responsible for issuing:
— a Wait For Event instruction when waiting for a spin-lock, to enter the low-power state
— a Send Event instructions when releasing a spin-lock.
The mechanism depends on the interaction of:
WFE wake-up events, see WFE wake-up events
the Event Register, see The Event Register on page B1-46
the Send Event instruction, see The Send Event instruction on page B1-46
the Wait For Event instruction, see The Wait For Event instruction on page B1-46.
WFE wake-up events
The following events are WFE wake-up events:
the execution of an SEV instruction on any processor in the multiprocessor system
an IRQ interrupt, unless masked by the CPSR.I bit
an FIQ interrupt, unless masked by the CPSR.F bit
an asynchronous abort, unless masked by the CPSR.A bit
a debug event, if invasive debug is enabled and the debug event is permitted.
For details of the masking bits in the CPSR see Format of the CPSR and SPSRs on page B1-16. This
masking is an important consideration with this mechanism, because lock mechanisms can be required
when interrupts are disabled.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-45