ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Bit [20] RAZ/SBZP.
Protected Memory System Architecture (PMSA)
DZ, bit [19] Divide by Zero fault enable bit. Any ARMv7-R implementation includes instructions to
perform unsigned and signed division, see SDIV on page A8-310 and UDIV on
page A8-468. This bit controls whether an integer divide by zero causes an Undefined
Instruction exception:
0 Divide by zero returns the result zero, and no exception is taken
1 Attempting a divide by zero causes an Undefined Instruction exception on the
SDIV or UDIV instruction.
Bit [18] RAO/SBOP.
BR, bit [17] Background Region bit. When the MPU is enabled this bit controls how an access that does
not map to any MPU memory region is handled:
0 Any access to an address that is not mapped to an MPU region generates a
Background Fault memory abort. This is the PMSAv6 behavior.
1 The default memory map is used as a background region:
A privileged access to an address that does not map to an MPU region
takes the properties defined for that address in the default memory map.
An unprivileged access to an address that does not map to an MPU region
generates a Background Fault memory abort.
For more information, see Using the default memory map as a background region on
page B4-5.
Bit [16] RAO/SBOP.
Bit [15] RAZ/SBZP.
RR, bit [14] Round Robin bit. If the cache implementation supports the use of an alternative replacement
strategy that has a more easily predictable worst-case performance, this bit selects it:
0 Normal replacement strategy, for example, random replacement
1 Predictable strategy, for example, round-robin replacement.
The RR bit must reset to 0.
The replacement strategy associated with each value of the RR bit is IMPLEMENTATION
DEFINED.
If the implementation does not support multiple IMPLEMENTATION DEFINED replacement
strategies this bit is RAZ/WI.
V, bit [13] Vectors bit. This bit selects the base address of the exception vectors:
0 Normal exception vectors, base address 0x00000000.
1 High exception vectors (Hivecs), base address 0xFFFF0000.
For more information, see Exception vectors and the exception base address on page B1-30.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-47