ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.288 VCLS
Vector Count Leading Sign Bits counts the number of consecutive bits following the topmost bit, that are
the same as the topmost bit, in each element in a vector, and places the results in a second vector. The count
does not include the topmost bit itself.
The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit signed integers.
The result vector elements are the same data type as the operand vector elements.
Encoding T1 / A1 Advanced SIMD
VCLS. ,
VCLS. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 D 1 1 size 0 0 Vd 0 1 0 0 0 Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 0 0 0 Q M 0 Vm
if size == ‘11’ then UNDEFINED;
if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’) then UNDEFINED;
esize = 8