ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Note
The XN bit, bit [12], is always valid in the IRACR.
If you access this register when the RGNR does not point to a valid region in the MPU instruction address
map, the result is UNPREDICTABLE.
Accessing the IRACR
To access the IRACR you read or write the CP15 registers with set to 0, set to c6, set to
c1, and set to 5. For example:
MRC p15,0,,c6,c1,5 ; Read CP15 Instruction Region Access Control Register
MCR p15,0,,c6,c1,5 ; Write CP15 Instruction Region Access Control Register
c6, MPU Region Number Register (RGNR)
The MPU Region Number Register, RGNR, defines the current memory region in:
the MPU data or unified address map
the MPU instruction address map, if the MPU implements separate data and instruction address
maps.
The value in the RGNR identifies the memory region description accessed by the Region Base Address, Size
and Enable, and Access Control Registers.
Note
There is only a single MPU Region Number Register. When the MPU implements separate data and
instruction address maps, the current region number is always identical for both address maps. This might
mean that the current region number is valid for one address map but invalid for the other map.
The RGNR is:
a 32-bit read/write register
accessible only in privileged modes.
The format of the RGNR is:
31 N N-1 0
Bit [31:N] UNK/SBZP.
Region, bits [N-1:0]
UNK/SBZP Region
The number of the current region in the Data or Unified address map, and in the Instruction
address map if the MPU implements separate Data and Instruction address maps.
The value of N is Log2(Number of regions supported) rounded up to an integer.
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