ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Access
mode a
Non-
blocking
Flag b
Flag
value Action
Debug Registers Reference
Table C10-10 Behavior of write accesses to DBGITR
New
InstrCompl
New
InstrCompl_l
InstrCompl_l 0 Write is ignored Unchanged Unchanged
1 Issue instruction c 0 c 0 c
Stall InstrCompl 0 Stall until (InstrCompl = 0) - -
1 Issue instruction c 0 c 0 c
Fast Not applicable - Save instruction in DBGITR d - -
a. For more information, see Access controls on the external view of the DCC registers and DBGITR, v7 Debug only
on page C10-21.
b. This column indicates which flag controls the access. The access does not depend on the value of any other flag.
c. If DBGDSCR.SDABORT_l, the Sticky Synchronous Data Abort bit, is set to 1, the instruction is not issued and
InstrCompl remains unchanged. For a description of the DBGDSCR.SDABORT_l bit, see Debug Status and
Control Register (DBGDSCR) on page C10-10.
d. The instruction is saved in the DBGITR and is issued on a read of DBGDTRTXext or a write of DBGDTRRXext.
For more information, see Access controls on the external view of the DCC registers and DBGITR, v7 Debug only
on page C10-21.
If the write is made through the memory-mapped interface and the Software Lock is set to 1, writes to the
DBGITR are ignored and have no other side-effects. This means that:
the DBGITR, and the InstrCompl and InstrCompl_l flags, remain unchanged
no instruction is issued.
For more information, see Permission summaries for memory-mapped and external debug interfaces on
page C6-45.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-47