ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
G.6 System level memory model
The pseudocode listed in Aligned memory accesses on page B2-31 and Unaligned memory accesses on
page B2-32 covers the alignment behavior of all architecture variants from ARMv4. ARMv6 supports two
alignment models, and the SCTLR.U bit controls the alignment configuration. For more information, see
Alignment on page AppxG-6.
Note
ARMv4 and ARMv5 only support the SCTLR.U = 0 alignment model.
ARMv7 only supports the SCTLR.U = 1 alignment model.
The following sections describe the system level memory model:
Endian configuration and control
Cache support on page AppxG-21
Tightly Coupled Memory (TCM) support on page AppxG-23
Virtual memory support on page AppxG-24
Protected Memory System Architecture (PMSA) on page AppxG-28.
G.6.1 Endian configuration and control
Endian control and configuration is supported by two bits in the CP15 SCTlR, and a PSR flag bit:
SCTLR.B BE-32 configuration bit. This bit must be RAZ/WI when BE-32 is not supported. BE-32 is
the legacy big endian model. See Endian support on page AppxG-7.
SCTLR.EE This bit is used to update CPSR.E on exception entry and provide endian model information
for translation table walks.
CPSR.E The flag is updated on exception entry to the value of the SCTLR.EE bit. Otherwise it is
controlled by the SETEND instruction. Writing the bit using an MSR instruction is deprecated in
ARMv6.
Note
BE and BE-32 are mutually exclusive. When SCTLR.B is set, SCTLR.EE and CPSR.E must be clear,
otherwise the endian behavior is UNPREDICTABLE.
Endian behavior can be configured on reset using the CFGEND[1:0] pins. Table G-3 on page AppxG-21
defines the CFGEND[1:0] encoding and associated configurations.
AppxG-20 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B