ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Programmers’ Model
The format of the JIDR is:
31 28 27 20 19 12 11 0
Architecture Implementer Subarchitecture SUBARCHITECTURE DEFINED
Architecture, bits [31:28]
Architecture code. This uses the same Architecture code that appears in the Main ID register
in coprocessor 15, see c0, Main ID Register (MIDR) on page B3-81 (VMSA
implementation) or c0, Main ID Register (MIDR) on page B4-32 (PMSA implementation).
Implementer, bits [27:20]
Implementer code of the designer of the subarchitecture. This uses the same Implementer
code that appears in the Main ID register in coprocessor 15, see c0, Main ID Register
(MIDR) on page B3-81 (VMSA implementation) or c0, Main ID Register (MIDR) on
page B4-32 (PMSA implementation).
If the trivial implementation of the Jazelle extension is used, the Implementer code is 0x00.
Subarchitecture, bits [19:12]
Contain the subarchitecture code. The following subarchitecture code is defined:
0x00 Jazelle v1 subarchitecture, or trivial implementation of Jazelle extension if
Implementer code is 0x00.
bits [11:0] Contain additional SUBARCHITECTURE DEFINED information.
To access the JIDR, read the CP14 registers with an MRC instruction with set to 7, set to c0,
set to c0, and set to 0. For example:
MRC p14, 7, , c0, c0, 0 ; Read Jazelle ID register
Jazelle Main Configuration Register (JMCR)
The Jazelle Main Configuration Register (JMCR) controls the Jazelle extension.
The JMCR is:
a CP14 register
a 32-bit register, with access rights that depend on the current privilege:
— for privileged operations the register is read/write
— for unprivileged operations, the register is normally write-only
when the Security Extensions are implemented, a Common register, see Common CP15 registers on
page B3-74.
For more information about unprivileged access restrictions see Access to Jazelle registers on page A2-78.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A2-77