ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
R, bit [0] Block Prefetch Running
0 No prefetch in operation
1 Prefetch in operation.
G.7.11 c7, Miscellaneous functions
The Wait For Interrupt operation is used in some implementations as part of a power management support
scheme. The operation is deprecated in ARMv6 and not supported in ARMv7, where it behaves as a NOP
instruction.
Barrier operations are used for system correctness to ensure visibility of memory accesses to other agents
in a system. Barrier functionality was formally defined as part of the memory architecture enhancements
introduced in ARMv6. The definitions are the same as for ARMv7. For details see Memory barriers on
page A3-47.
Table G-10 summarizes the MCR instruction encoding details.
G.7.12 c7, VMSA virtual to physical address translation support
If the Security Extensions are implemented in ARMv6K, virtual to physical address translation support is
provided as described in CP15 c7, Virtual Address to Physical Address translation operations on
page B3-130.
G.7.13 c8, VMSA TLB support
Table G-10 memory barrier register support
Operation CRn opc1 CRm opc2
Wait For Interrupt (CP15WFI) c7 0 c0 4
Instruction Synchronization Barrier (CP15ISB) a
Data Synchronization Barrier (CP15DSB) b
c7 0 c5 4
c7 0 c10 4
Data Memory Barrier (CP15DMB) c7 0 c10 5
a. This operation was previously known as Prefetch Flush (PF or PFF).
b. This operation was previously known as Data Write Barrier or Drain Write Buffer (DWB).
CP15 TLB operation provision in ARMv6 is the same as for ARMv7-A. For details see TLB maintenance
on page B3-56 and CP15 c8, TLB maintenance operations on page B3-138.
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