ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
C5.8 Memory system behavior in Debug state
The Debug architecture places requirements on the memory system. There are two general guidelines:
Memory coherency has to be maintained during debugging.
It is best if debugging is non-intrusive. This requires a way to preserve, for example, the contents of
memory caches and translation lookaside buffers (TLBs), so the state of the target application is not
altered.
In Debug state, it is strongly recommended that the caches and TLBs, where implemented, behave as
described here. For preservation purposes it is strongly recommended that it is possible to:
disable cache evictions and linefills, so that cache accesses, on read or write, do not cause the contents
of caches to change.
disable TLB evictions and replacements, so that translations do not cause the contents of TLBs to
change.
The mechanisms for disabling these operations:
must be accessible by the external debugger
are only required when in Debug state.
In v6.1 Debug and v7 Debug, the Debug State Cache Control Register (DBGDSCCR) and the Debug State
MMU Control Register (DBGDSMCR) are used for this purpose.
While the processor is in Debug state, no instruction fetches occur and therefore:
if the system implements separate instruction and data caches then there might be no instruction
cache evictions or replacements
if the system implements separate instruction and data TLBs then there might be no instruction TLB
evictions or replacements.
In Debug state, reads must behave as in Non-debug state:
cache reads return data from the cache
cache misses fetch from external memory.
A debugger must be able to maintain coherency between instruction and data memory, and maintain
coherency in a multiprocessor system. This means that in Debug state a debugger must be able to force all
writes to update all levels of memory to the point of coherency.
It must be possible to reset the memory system of the processor to a known safe and coherent state. Also, it
must be possible to reset any caches of meta-information, such as branch predictor arrays, to a safe and
coherent state.
For debugging purposes ARM recommends that TLBs can be disabled so that all TLB accesses are read
from the main translation tables, and not from the TLB. This enables a debugger to access memory without
using any virtual to physical memory mapping that is implemented for the application.
C5-24 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B