ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.2.10 Synchronization primitives
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 op 1 0 0 1
Table A5-12 shows the allocation of encodings in this space.
Other encodings in this space are UNDEFINED.
Table A5-12 Synchronization primitives
op Instruction See Variant
0x00 Swap Word, Swap Byte SWP, SWPB on page A8-432 a
1000 Store Register Exclusive STREX on page A8-400 v6
1001 Load Register Exclusive LDREX on page A8-142 v6
1010 Store Register Exclusive Doubleword STREXD on page A8-404 v6K
1011 Load Register Exclusive Doubleword LDREXD on page A8-146 v6K
1100 Store Register Exclusive Byte STREXB on page A8-402 v6K
1101 Load Register Exclusive Byte LDREXB on page A8-144 v6K
1110 Store Register Exclusive Halfword STREXH on page A8-406 v6K
1111 Load Register Exclusive Halfword LDREXH on page A8-148 v6K
a. Use of these instructions is deprecated.
A5-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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