ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Events
As a result, for an instruction that modifies the context in which the processor tests for debug events, the
processor must test for all possible debug event in terms of the context before the memory access operation
is observed or the instruction executes. For example:
In a v7 Debug implementation that uses the memory-mapped interface, a write to the DBGWCR to
enable a watchpoint on a Data Virtual Address (DVA) of the DBGWCR itself must not trigger the
watchpoint.
Conversely, a write to the DBGWCR to disable the same watchpoint must trigger the watchpoint. For
more information, see Debug events in the debug monitor on page C3-26.
An instruction that writes to a Breakpoint Control Register (DBGBCR) or Vector Catch Register
(DBGVCR) to enable a debug event on the Instruction Virtual Address (IVA) of the instruction itself
must not trigger the debug event.
Conversely, a write to the DBGBCR or DBGVCR to disable the same debug event must trigger the
debug event.
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