ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

System Instructions
B6.1.7 MSR (register)
Move to Special Register from ARM core register moves the value of a general-purpose register to the
CPSR or the SPSR of the current mode.
Encoding T1 ARMv6T2, ARMv7
MSR ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 0 R Rn 1 0 (0) 0 mask (0)(0)(0)(0)(0)(0)(0)(0)
n = UInt(Rn); write_spsr = (R == ‘1’);
if mask == ‘0000’ then UNPREDICTABLE;
if BadReg(n) then UNPREDICTABLE;
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
MSR ,
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 R 1 0 mask (1)(1)(1)(1)(0)(0)(0)(0) 0 0 0 0 Rn
n = UInt(Rn); write_spsr = (R == ‘1’);
if mask == ‘0000’ then UNPREDICTABLE;
if n == 15 then UNPREDICTABLE;
Assembler syntax
MSR ,
where:
See Standard assembler syntax fields on page A8-7.
Is one of:
• APSR_
• CPSR_
• SPSR_.
ARM recommends the APSR forms when only the N, Z, C, V, Q, and GE[3:0] bits are being
written. For more information, see The Application Program Status Register (APSR) on
page A2-14.
Is the general-purpose register to be transferred to .
Is one of nzcvq, g, or nzcvqg.
In the A and R profiles:
APSR_nzcvq is the same as CPSR_f (mask == ’1000’)
APSR_g is the same as CPSR_s (mask == ’0100’)
APSR_nzcvqg is the same as CPSR_fs (mask == ’1100’).
B6-14 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B