ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
G.3.3 Semaphore support
ARM deprecates the use of the ARM semaphore instructions SWP and SWPB, in favour of the exclusive access
mechanism described in Synchronization and semaphores on page A3-12:
ARMv6 and ARMv6T2 support the LDREX and STREX instructions
ARMv6K and ARMv7 add the CLREX, LDREXB, LDREXD, LDREXH, STREXB, STREXD, and STREXH instructions.
All Load-Exclusive and Store-Exclusive access instructions must be naturally aligned. An unaligned
Exclusive access instruction generates an unaligned access Data Abort exception.
G.3.4 Memory model and memory ordering
The memory model was formalized in ARMv6. This included:
defining Normal, Device, and Strongly-ordered memory types
adding a Shareable memory attribute
extending the memory attributes to support two cache policies, associated with Inner and Outer levels
of cache and including a write allocation hint capability
adding Data Memory Barrier (DMB) and Data Synchronization Barrier (DSB) operations, to
support the formalized memory ordering requirements
adding an Instruction Synchronization Barrier (ISB) operation, to guarantee that instructions
complete before any instructions that come after them in program order are executed.
ARMv6 provided barrier operations as CP15 c7 operations. These migrated to the ARM and Thumb
instruction sets as follows:
ARMv6 required DMB, DSB, and ISB operations in CP15, see c7, Miscellaneous functions on
page AppxH-51. The functionality of these operations is the same as that described for ARMv7 in
Memory barriers on page A3-47.
ARMv7 adds DMB, DSB, and ISB instructions to the ARM and Thumb instruction sets.
ARM deprecates use of the CP15 barrier operations.
Ordering of instructions that change the CPSR interrupt masks
In ARMv6, any instruction that implicitly or explicitly changes the interrupt masks in the CPSR and appears
in program order after a Strongly-ordered access must wait for the Strongly-ordered memory access to
complete. These instructions are:
An MSR with the control field mask bit set.
The flag-setting variants of arithmetic and logical instructions with the PC as the destination register.
These instructions copy the SPSR to CPSR.
AppxG-8 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B