ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
A1
It is impossible for an observer in the shareability domain of a memory location to
observe two reads to the same memory location performed by the same observer in
an order that would not occur in a sequential execution of a program.
In Figure A3-4, an access refers to a read or a write access to the specified memory type.
For example, Device access, Non-shareable refers to a read or write access to Non-shareable
Device memory.
There are no ordering requirements for implicit accesses to any type of memory.
Program order for instruction execution
Figure A3-4 Memory ordering restrictions
The program order of instruction execution is the order of the instructions in the control flow trace.
Explicit memory accesses in an execution can be either:
Strictly Ordered
Denoted by