ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C5.3 Behavior of the PC and CPSR in Debug state
Debug event
Debug State
Processing is halted on entry to Debug state, see Entering Debug state on page C5-3. After the processor
has entered Debug state, a read of the PC returns a return address plus an offset. The return address depends
on the type of debug event, and the offset depends on the instruction set state of the processor when Debug
state was entered. Table C5-1 shows the values returned by a read of the PC.
PC value, for instruction set state on Debug entry
ARM
Thumb or
ThumbEE
Jazelle b
Table C5-1 PC value while in Debug state
Meaning of return address
(RA) a obtained from PC read
Breakpoint RA + 8 RA + 4 RA + Offset Breakpointed instruction address
Synchronous
Watchpoint
Asynchronous
Watchpoint
BKPT
instruction
RA + 8 RA + 4 RA + Offset Address of the instruction that
triggered the watchpoint c
RA + 8 RA + 4 RA + Offset Address of the instruction for the
execution to resume d
RA + 8 RA + 4 RA + Offset BKPT instruction address
Vector Catch RA + 8 RA + 4 RA + Offset Vector address
External Debug
Request
RA + 8 RA + 4 RA + Offset Address of the instruction for the
execution to resume
Halt Request RA + 8 RA + 4 RA + Offset Address of the instruction for the
execution to resume
OS Unlock
Catch
RA + 8 RA + 4 RA + Offset Address of the instruction for the
execution to resume
a. Return address (RA) is the address of the first instruction that the processor must execute on exit from Debug state. This
enables program execution to continue from where it stopped.
b. Offset is an IMPLEMENTATION DEFINED value that is constant and documented.
c. Returning to RA has the effect of retrying the instruction. This can have implications under the memory order model.
See Synchronous and Asynchronous Watchpoint debug events on page C3-18.
d. RA is not the address of the instruction that triggered the watchpoint, but one that was executed some number of
instructions later. The address of the instruction that triggered the watchpoint can be discovered from the value in the
DBGWFAR. See Watchpoint Fault Address Register (DBGWFAR) on page C10-28.
On entry to Debug state, the value of the CPSR is the value that the instruction at the return address would
have been executed with, if it had not been cancelled by the debug event.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C5-7