ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
The TLB Type ID Register and the Multiprocessor Affinity Register are as defined for ARMv7, see:
c0, TLB Type ID Register (TLBTR)
c0, Multiprocessor Affinity Register (MPIDR) on page B3-87.
The MPU Type Register is as defined for ARMv7, see c0, MPU Type Register (MPUIR) on page B4-36. In
an ARMv6 PMSA implementation, if the MPU is not implemented use of the default memory map is
optional.
c0, TCM Type Register (TCMTR)
The TCMTR must be implemented in ARMv6 and ARMv7. In ARMv7, the register can have a different
format from that given here, see c0, TCM Type Register (TCMTR) on page B3-85.
In ARMv7, TCM support is IMPLEMENTATION DEFINED. For ARMv6, see c9, TCM support on
page AppxG-46 and c9, TCM Non-Secure Access Control Registers, DTCM-NSACR and ITCM-NSACR on
page AppxG-51 where the Security Extensions are supported.
31 29 28 19 18 16 15 3 2 0
0 0 0 Reserved DTCM Reserved ITCM
Bits [31:29] Set to 0b000 before ARMv7.
Bits [28:19,15:3]
Reserved.
DTCM, Bits [18:16] Indicate the number of Data TCMs implemented. This value lies in the range 0 to 4,
0b000 to 0b100. All other values are reserved.
ITCM, Bits [2:0] Indicate the number of Instruction or Unified TCMs implemented. This value lies
in the range 0 to 4, 0b000 to 0b100. All other values are reserved.
c0, TLB Type ID Register (TLBTR)
Instruction TCMs are accessible to both instruction and data sides.
In an ARMv6 VMSA implementation the TLB Type Register, TLBTR, is a read-only register that defines
whether the implementation provides separate instruction and data TLBs, or a unified TLB. It also defines
the number of lockable TLB entries. The ARMv7-A description of the register describes the general features
of the register and how to access it. See c0, TLB Type Register (TLBTR) on page B3-86. However, the
register format is different in ARMv6. The ARMv6 format of the TLBTR is:
31 24 23 16 15 8 7 1 0
Reserved I_nlock D_nlock Reserved nU
Bits [31:24, 7:1] Reserved, UNK.
I_nlock, bits [23:16] Number of lockable entries in the instruction TLB. The value of this field gives the
number of lockable entries, between 0b00000000 for no lockable entries, and
0b11111111 for 255 lockable entries.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-33