ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
Asynchronous abort
The behavior depends on the Debug architecture version:
v6.1 Debug, v7 Debug
When an asynchronous abort is signalled in Debug state, no Data Abort
exception is generated and the processor behaves as follows:
The setting of the CPSR.A bit is ignored.
PC, CPSR, SPSR_abt, LR_abt, SCR.NS, and DBGDSCR.MOE are
unchanged.
The processor remains in Debug state.
The DFSR is unchanged.
If DBGDSCR.ADAdiscard is 1:
— DBGDSCR.ADABORT_l, the Sticky Asynchronous Data Abort
bit, is set to 1.
— On exit from Debug state, this asynchronous abort is not acted on.
— If the ISR is implemented, the ISR.A bit is not changed, because
no abort is pended.
If DBGDSCR.ADAdiscard is 0:
— In v7 Debug, DBGDSCR.ADABORT_l is unchanged.
— In v6.1 Debug, DBGDSCR.ADABORT_l is set to 1.
— On exit from Debug state, this asynchronous abort is acted on.
— If the asynchronous abort is an external asynchronous abort, and
the ISR is implemented, the ISR.A bit is set to 1 indicating that an
external abort is pending.
See also:
Asynchronous aborts and entry to Debug state on page C5-5.
the descriptions of the ADABORT_l and ADAdiscard bits in Debug
Status and Control Register (DBGDSCR) on page C10-10.
v6 Debug When an asynchronous abort is signalled in Debug state, then:
if the CPSR.A bit is 0, the abort is generated when the CPSR.A bit is
cleared to 0
if the CPSR.A bit is 1, a Data Abort exception is generated, see
Undefined Instruction and Data Abort exceptions in Debug state in
v6 Debug on page C5-23.
C5-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B