ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
Instruction Details
VSWP{.} , Encoded as Q = 1, size = ’00’
VSWP{.} , Encoded as Q = 0, size = ’00’
where:
See Standard assembler syntax fields on page A8-7. An ARM VSWP instruction must be
unconditional.
An optional data type. It is ignored by assemblers, and does not affect the encoding.
, The vectors for a quadword operation.
, The vectors for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
if d == m then
D[d+r] = bits(64) UNKNOWN;
else
tmp = D[d+r];
D[d+r] = D[m+r];
D[m+r] = tmp;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-797