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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Application Level Programmers’ Model<br />

ThumbEE H<strong>and</strong>ler Base Register. This contains the base address for ThumbEE h<strong>and</strong>lers.<br />

A h<strong>and</strong>ler is a short, commonly executed, sequence of instructions. It is typically, but not always,<br />

associated directly with one or more bytecodes or other intermediate language elements.<br />

Changes to these CP14 registers have the same synchronization requirements as changes to the CP15<br />

registers. These are described in:<br />

Changes to CP15 registers <strong>and</strong> the memory order model on page B3-77 for a VMSA implementation<br />

Changes to CP15 registers <strong>and</strong> the memory order model on page B4-28 for a PMSA implementation.<br />

ThumbEE is an unprivileged, user-level facility, <strong>and</strong> there are no special provisions for using it securely. For<br />

more information, see ThumbEE <strong>and</strong> the Security Extensions on page B1-73.<br />

ThumbEE Configuration Register (TEECR)<br />

The ThumbEE Configuration Register (TEECR) controls unprivileged access to the ThumbEE H<strong>and</strong>ler<br />

Base Register.<br />

The TEECR is:<br />

a CP14 register<br />

a 32-bit register, with access rights that depend on the current privilege:<br />

— the result of an unprivileged write to the register is UNDEFINED<br />

— unprivileged reads, <strong>and</strong> privileged reads <strong>and</strong> writes, are permitted.<br />

when the Security Extensions are implemented, a Common register.<br />

The format of the TEECR is:<br />

31 1 0<br />

UNK/SBZP XED<br />

Bits [31:1] UNK/SBZP.<br />

XED, bit [0] Execution Environment Disable bit. Controls unprivileged access to the ThumbEE H<strong>and</strong>ler<br />

Base Register:<br />

0 Unprivileged access permitted.<br />

1 Unprivileged access disabled.<br />

The reset value of this bit is 0.<br />

The effects of a write to this register on ThumbEE configuration are only guaranteed to be visible to<br />

subsequent instructions after the execution of an ISB instruction, an exception entry or an exception return.<br />

However, a read of this register always returns the value most recently written to the register.<br />

To access the TEECR, read or write the CP14 registers with an MRC or MCR instruction with set to 6,<br />

set to c0, set to c0, <strong>and</strong> set to 0. For example:<br />

MRC p14, 6, , c0, c0, 0 ; Read ThumbEE Configuration Register<br />

MCR p14, 6, , c0, c0, 0 ; Write ThumbEE Configuration Register<br />

A2-70 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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