ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Thumb Instruction Set Encoding
A6.3.8 Load halfword, memory hints
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 op1 0 1 1 Rn Rt op2
Table A6-19 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
Except where otherwise noted, these encodings are available in ARMv6T2 and above.
op1 op2 Rn Rt Instruction See
Table A6-19 Load halfword, preload
0x - 1111 not 1111 Load Register Halfword LDRH (literal) on page A8-154
01 - not 1111 not 1111 Load Register Halfword LDRH (immediate, Thumb) on
page A8-150
00 1xx1xx not 1111 not 1111
1100xx not 1111 not 1111
1110xx not 1111 not 1111 Load Register Halfword
Unprivileged
LDRHT on page A8-158
000000 not 1111 not 1111 Load Register Halfword LDRH (register) on page A8-156
1x - 1111 not 1111 Load Register Signed
Halfword
11 - not 1111 not 1111 Load Register Signed
10 1xx1xx not 1111 not 1111
Halfword
1100xx not 1111 not 1111
1110xx not 1111 not 1111 Load Register Signed
Halfword Unprivileged
000000 not 1111 not 1111 Load Register Signed
Halfword
0x - 1111 1111 UNPREDICTABLE -
01 - not 1111 1111 Preload Data with intent to
Write a
00 1100xx not 1111 1111 Preload Data with intent to
Write a
000000 not 1111 1111 Preload Data with intent to
Write a
LDRSH (literal) on page A8-170
LDRSH (immediate) on page A8-168
LDRSHT on page A8-174
LDRSH (register) on page A8-172
PLD, PLDW (immediate) on
page A8-236
PLD, PLDW (immediate) on
page A8-236
PLD, PLDW (register) on
page A8-240
A6-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B