ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
B2.1 About the memory system architecture
The ARM architecture supports different implementation choices for the memory system microarchitecture
and memory hierarchy, depending on the requirements of the system being implemented. In this respect, the
memory system architecture describes a design space in which an implementation is made. The architecture
does not prescribe a particular form for the memory systems. Key concepts are abstracted in a way that
enables implementation choices to be made while enabling the development of common software routines
that do not have to be specific to a particular microarchitectural form of the memory system. For more
information about the concept of a hierarchical memory system see Memory hierarchy on page A3-52.
B2.1.1 Form of the memory system architecture
ARMv7 supports different forms of the memory system architecture, that map onto the different architecture
profiles. Two of these are described in this manual:
ARMv7-A, the A profile, requires the inclusion of a Virtual Memory System Architecture (VMSA),
as described in Chapter B3 Virtual Memory System Architecture (VMSA).
ARMv7-R, the R profile, requires the inclusion of a Protected Memory System Architecture (PMSA),
as described in Chapter B4 Protected Memory System Architecture (PMSA).
Both of these memory system architectures provide mechanisms to split memory into different regions.
Each region has specific memory types and attributes. The two memory system architectures have different
capabilities and programmers’ models.
The memory system architecture model required by ARMv7-M, the M profile, is outside the scope of this
manual. It is described in the ARMv7-M Architecture Reference Manual.
B2.1.2 Memory attributes
Summary of ARMv7 memory attributes on page A3-25 summarizes the memory attributes, including how
different memory types have different attributes. Each region of memory has a set of memory attributes:
B2.1.3 Levels of cache
in a PMSA implementation the attributes are part of each MPU memory region definition
in a VMSA implementation the translation table entry that defines a virtual memory region also
defines the attributes for that region.
From ARMv7, the architecturally-defined cache control mechanism covers multiple levels of cache, as
described in Caches on page B2-3. Also, it permits levels of cache beyond the scope of these cache control
mechanisms, see System-level caches on page B2-26.
Note
Before ARMv7, the architecturally-defined cache control mechanism covers only a single level of cache,
and any support for other levels of cache is IMPLEMENTATION DEFINED.
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