ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.4 Address mapping restrictions
Virtual Memory System Architecture (VMSA)
ARMv6 supported a page coloring restriction that, when implemented, required all Virtual Address aliases
of a given Physical Address to have the same value for address bits [13:12]. This page coloring restriction
was required to support Virtually Index Physically Tagged (VIPT) caches with a cache way size larger than
4KBytes. For details of the page coloring restriction see Virtual to physical translation mapping restrictions
on page AppxG-26.
ARMv7 does not support page coloring, and requires that all data and unified caches behave as Physically
Indexed Physically Tagged (PIPT) caches.
Note
An ARMv7 implementation might use techniques such as hardware alias avoidance to make a VIPT cache
behave as a PIPT cache, and might improve performance by avoiding accesses to frequently alternating
aliases to a physical address. Such approaches give good results, but ARM recommends migration to the
use of true PIPT caches for all data and unified caches.
In an ARMv7 implementation, any data or unified cache maintenance operation that operates on a virtual
address must take account of the fact that the cache behaves as a PIPT cache. This means that the
implementation must perform the appropriate action on the physical address that corresponds to the MVA
targeted by the operation.
The ARMv7 requirements for instruction caches are described in Requirements for instruction caches.
B3.4.1 Requirements for instruction caches
In a base VMSAv7 implementation, the following conditions require cache maintenance of an instruction
cache:
writing new data to an instruction address
writing new address mappings to the translation table
changing one or more of the TTBR0, TTBR1 and TTBCR registers without changing the ASID
enabling or disabling the MMU, by writing to the SCTLR.
Note
These conditions are consistent with the maintenance required for an ASID-tagged Virtually Indexed
Virtually Tagged (VIVT) instruction cache that also includes a security status bit for each cache entry.
VMSAv7 can be implemented with an optional extension, the IVIPT extension (Instruction cache Virtually
Indexed Physically Tagged extension). The effect of this extension is to reduce the instruction cache
maintenance requirement to a single condition:
writing new data to an instruction address.
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