ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
ARMv6T2 supports the full Thumb instruction set, apart from a few instructions that are introduced in
ARMv7.
Interworking
In ARMv6, the instructions that provide interworking branches between ARM and Thumb states are:
BL and BLX
LDR, LDM, and POP instructions that load the PC.
In ARMv7, the following ARM instructions also perform interworking branches if their destination register
is the PC and the ’S’ option is not specified:
ADC, ADD, AND, ASR, BIC, EOR, LSL, LSR, MOV, MVN, ORR, ROR, RRX, RSB, RSC, SBC, and SUB.
The instructions do not perform interworking branches in ARMv6, and the corresponding Thumb
instructions do not perform interworking branches in either ARMv6 or ARMv7. This functionality is
described by the ALUWritePC() pseudocode function. See Pseudocode details of operations on ARM core
registers on page A2-12.
BL and BLX (immediate) instructions, before ARMv6T2
In ARMv4T, ARMv5T, ARMv5TE, ARMv5TEJ, ARMv6, and ARMv6K, the BL and BLX (immediate)
instructions are the only 32-bit Thumb instructions, and the maximum range of the branches that they
specify is restricted to approximately +/-4MB. This means that each of the two halfwords of these
instructions has top five bits 0b11101, 0b11110, or 0b11111, and makes it possible to execute the two
halfwords as separate 16-bit instructions.
The following descriptions use the format described in Instruction encodings on page A8-2, except that
they:
name the encodings H1, H2 and H3
have pseudocode that defines the entire operation of the instruction, instead of separate
encoding-specific pseudocode and Operation pseudocode.
When the two halfwords of a BL or BLX (immediate) instruction are executed separately, their behavior is as
follows:
Encoding H1 ARMv4T, ARMv5T*, ARMv6, ARMv6K Used for BL and BLX
BL{X} First of two 16-bit instructions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 imm11
LR = PC + SignExtend(imm11:Zeros(12), 32);
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