ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common VFP Subarchitecture Specification
The trigger instruction might not be the VFP instruction immediately following the exceptional instruction,
and depending on the instruction sequence, the bounce can occur many instructions later. An
implementation can continue to execute some VFP instructions before detecting the exceptional condition,
provided:
these instructions are not themselves exceptional
these instructions are independent of the exceptional instruction
the operands for the exceptional instruction are still available after the execution of the instructions.
Determination of the trigger instruction
VMSR and VMRS instructions that access the FPEXC, FPSID, FPINST or FPINST2 registers do not trigger
exception processing.
These system registers are not used in normal VFP application code, but are designed for use by support
code and the operating system. Accesses to these registers do not bounce when the processor is in an
asynchronous exceptional state, indicated by FPEXC.EX == 1. This means the support code can read
information out of these registers, before clearing the exceptional condition by setting FPEXC.EX to 0.
All other VFP instructions, including VMSR and VMRS instructions that access the FPSCR, trigger exception
processing if there is an outstanding exceptional condition. For more information, see VFP support code on
page B1-70.
Exception processing for scalar instructions
When an exceptional condition is detected in a scalar CDP instruction:
the exception-generating instruction is copied to the FPINST Register, see The Floating-Point
Instruction Registers, FPINST and FPINST2 on page AppxB-20
the FPEXC.VECITR field is set to 0b111 to indicate that no short vector iterations are required
the FPEXC.EX bit is set to 1
all the operand registers to the instruction are restored to their original values, so that the instruction
can be re-executed in support code
If the execution of the instruction would set the cumulative exception flags for any exception,
hardware might or might not set these flags.
Note
Because the cumulative exception flags are cumulative, it is always acceptable for the support code
to set the exception flags to 1 as a result of emulating the instruction, even if the hardware has set
them.
If there is a bypassed instruction then this is copied to the FPINST2 Register, and the FPEXC.FP2V bit is
set to 1.
The next VFP instruction issued becomes the trigger instruction and causes entry to the operating system.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxB-7