ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ThumbEE
A9.1 The ThumbEE instruction set
In general, instructions in ThumbEE are identical to Thumb instructions, with the following exceptions:
A small number of instructions are affected by modifications to transitions from ThumbEE state. For
more information, see ThumbEE state transitions.
A substantial number of instructions have a null check on the base register before any other operation
takes place, but are identical (or almost identical) in all other respects. For more information, see Null
checking on page A9-3.
A small number of instructions are modified in additional ways. See Instructions with modifications
on page A9-4.
Three Thumb instructions, BLX (immediate), 16-bit LDM, and 16-bit STM, are removed in ThumbEE
state.
The encoding corresponding to BLX (immediate) in Thumb is UNDEFINED in ThumbEE state.
16-bit LDM and STM are replaced by new instructions, for details see Additional ThumbEE instructions
on page A9-14.
Two new 32-bit instructions, ENTERX and LEAVEX, are introduced in both the Thumb instruction set and
the ThumbEE instruction set. See Additional instructions in Thumb and ThumbEE instruction sets on
page A9-7. These instructions use previously UNDEFINED encodings.
A9.1.1 ThumbEE state transitions
Instruction set state transitions to ThumbEE state can occur implicitly as part of a return from exception, or
explicitly on execution of an ENTERX instruction.
Instruction set state transitions from ThumbEE state can only occur due to an exception, or due to a
transition to Thumb state using the LEAVEX instruction. Return from exception instructions (RFE and SUBS PC,
LR, #imm) are UNPREDICTABLE in ThumbEE state.
Any other Thumb instructions that can update the PC in ThumbEE state are UNPREDICTABLE if they attempt
to change to ARM state. Interworking of ARM and Thumb instructions is not supported in ThumbEE state.
The instructions affected are:
LDR, LDM, and POP instructions that write to the PC, if bit [0] of the value loaded to the PC is 0
BLX (register), BX, and BXJ, where Rm bit [0] == 0.
Note
SVC, BKPT, and UNDEFINED instructions cause an exception to occur.
If a BXJ instruction is executed in ThumbEE state, with Rm bit[0] == 1, it does not enter Jazelle state.
Instead, it behaves like the corresponding BX instruction and remains in ThumbEE state.
Debug state is a special case. For the rules governing changes to CPSR state bits and Debug state, see
Executing instructions in Debug state on page C5-9.
A9-2 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B