ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

next_instr_addr = PC - 2;
BranchWritePC(LR + ZeroExtend(imm11:’0’, 32));
LR = next_instr_addr : ‘1’;
if op == ‘0’ then
next_instr_addr = PC - 2;
SelectInstrSet(InstrSet_ARM);
BranchWritePC(Align(LR,4) + ZeroExtend(imm10:’00’, 32));
LR = next_instr_addr;
else
UNDEFINED;
ARMv6 Differences
Encoding H2 ARMv4T, ARMv5T*, ARMv6, ARMv6K Used for BL
BL Second of two 16-bit instructions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 imm11
Encoding H3 ARMv5T*, ARMv6, ARMv6K Used for BLX
BLX Second of two 16-bit instructions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 imm10 op
An encoding H1 instruction must be followed by an encoding H2 or encoding H3 instruction. Similarly, an
encoding H2 or encoding H3 instruction must be preceded by an encoding H1 instruction. Otherwise, the
behavior is UNPREDICTABLE.
It is IMPLEMENTATION DEFINED whether processor exceptions can occur between the two instructions of a
BL or BLX pair. If they can, the ARM exception return instructions must be able to return correctly to the
second instruction of the pair. The exception handler does not have to take special precautions. See
Exception return on page B1-38 for the definition of exception return instructions.
Note
There are no Thumb exception return instructions in the architecture versions that support separate
execution of the two halfwords of BL and BLX (immediate) instructions. Also, the ARM RFE instruction is only
defined from ARMv6 onwards.
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