ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
The register containing the element to store. It must be {}. The register Dd is encoded
in D:Vd
Contains the base address for the access.
The alignment. It can be one of:
16 2-byte alignment, available only if is 16
32 4-byte alignment, available only if is 32
omitted Standard alignment, see Unaligned data access on page A3-5.
! If present, specifies writeback.
Contains an address offset applied after the access.
For more information about , !, and , see Advanced SIMD addressing mode on page A7-30.
Table A8-9 shows the encoding of index and alignment for different values.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
MemU[address,ebytes] = Elem[D[d],index,esize];
Exceptions
Undefined Instruction, Data Abort.
Table A8-9 Encoding of index and alignment
== 8 == 16 == 32
Index index_align[3:1] = x index_align[3:2] = x index_align[3] = x
omitted index_align[0] = 0 index_align[1:0] = ’00’ index_align[2:0] = ’000’
== 16 - index_align[1:0] = ’01’ -
== 32 - - index_align[2:0] = ’011’
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-771