ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Note
To avoid security holes, ARM strongly recommends that:
you do not change from Secure to Non-secure state by using an MSR or CPS instruction to switch from
Monitor mode to some other mode while SCR.NS is 1
you do not use an MCR instruction that writes SCR.NS to change from Secure to Non-secure state. This
means you should not alter the SCR.NS bit in any mode except Monitor mode.
The usual mechanism for changing from Secure to Non-secure state is an exception return.
Pseudocode details of Secure state operations
The HaveSecurityExt() function returns TRUE if the Security Extensions are implemented, and FALSE
otherwise.
The following function returns TRUE if the Security Extensions are not implemented or the processor is in
Secure state, and FALSE otherwise.
// IsSecure()
// ==========
boolean IsSecure()
return !HaveSecurityExt() || SCR.NS == ‘0’ || CPSR.M == ‘10110’; // Monitor mode
B1.5.2 Impact of the Security Extensions on the modes and exception model
This section summarizes the effect of the Security Extensions on the modes and exception model, to give a
overview of the Security Extensions. When the Security Extensions are implemented:
An additional mode, Monitor mode, is implemented. For more information, see ARM processor
modes on page B1-6 and Security states on page B1-25.
An additional exception, the Secure Monitor Call (SMC) exception, is implemented. This is
generated by the SMC instruction. For more information, see Secure Monitor Call (SMC) exception on
page B1-53 and SMC (previously SMI) on page B6-18.
Because the SCTLR is banked between the Secure and Non-secure states, the V and VE bits are
defined independently for the Secure and Non-secure states. For each state:
— the SCTLR.V bit controls whether the normal or the high exception vectors are used
— the SCTLR.VE bit controls whether the IRQ and FIQ vectors are IMPLEMENTATION DEFINED.
For more information, see Exception vectors and the exception base address on page B1-30.
The base address for the normal exception vectors is held in a CP15 register that is banked between
the two security states. This register defines the base address used for exceptions handled in modes
other than Monitor mode. Another CP15 register holds the base address for exceptions handled in
Monitor mode. For more information, see Exception vectors and the exception base address on
page B1-30.
B1-28 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B