ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
Cache lockdown
Cache lockdown requirements can conflict with the management of hardware coherency. For this reason,
ARMv7 introduces significant changes in this area, compared to previous versions of the ARM architecture.
These changes recognize that, in many systems, cache lockdown is inappropriate.
For an ARMv7 implementation:
There is no requirement to support cache lockdown.
If cache lockdown is supported, the lockdown mechanism is IMPLEMENTATION DEFINED. However
key properties of the interaction of lockdown with the architecture must be described in the
implementation documentation.
The Cache Type Register does not hold information about lockdown. This is a change from ARMv6.
However some CP15 c9 encodings are available for IMPLEMENTATION DEFINED, cache lockdown
features, see Implementation defined memory system features on page B2-27.
Note
For details of cache lockdown in ARMv6 see c9, Cache lockdown support on page AppxG-45.
B2.2.3 Cache enabling and disabling
Levels of cache on page B2-2 indicates that:
from ARMv7 the architecture defines the control of multiple levels of cache
before ARMv7 the architecture defines the control of only one level of cache.
This means the mechanism for cache enabling and disabling caches changes in ARMv7. In both cases,
enabling and disabling of caches is controlled by the SCTLR.C and SCTLR.I bits, see:
c1, System Control Register (SCTLR) on page B3-96, for a VMSA implementation
c1, System Control Register (SCTLR) on page B4-45, for a PMSA implementation.
In ARMv7:
The SCTLR.C bit enables or disables all data and unified caches, across all levels of cache visible to
the processor.
The SCTLR.I bit enables or disables all instruction caches, across all levels of cache visible to the
processor.
If an implementation requires finer-grained control of cache enabling it can implement control bits
in the Auxiliary Control Register for this purpose. For example, an implementation might define
control bits to enable and disable the caches at a particular level. For more information about the
Auxiliary Control Register see:
— c1, Implementation defined Auxiliary Control Register (ACTLR) on page B3-103, for a VMSA
implementation
— c1, Implementation defined Auxiliary Control Register (ACTLR) on page B4-50, for a PMSA
implementation.
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