ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.53 LDM / LDMIA / LDMFD
Load Multiple (Increment After) loads multiple registers from consecutive memory locations using an
address from a base register. The consecutive memory locations start at this address, and the address just
above the highest of those locations can optionally be written back to the base register. The registers loaded
can include the PC, causing a branch to a loaded address. Related system instructions are LDM (user
registers) on page B6-7 and LDM (exception return) on page B6-5.
Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)
LDM !, not included in
LDM , included in
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 Rn register_list
n = UInt(Rn); registers = ‘00000000’:register_list; wback = (registers == ‘0’);
if BitCount(registers) < 1 then UNPREDICTABLE;
Encoding T2 ARMv6T2, ARMv7
LDM.W {!},
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 1 0 W 1 Rn P M (0) register_list
if W == ‘1’ && Rn == ‘1101’ then SEE POP;
n = UInt(Rn); registers = P:M:’0’:register_list; wback = (W == ‘1’);
if n == 15 || BitCount(registers) < 2 || (P == ‘1’ && M == ‘1’) then UNPREDICTABLE;
if registers == ‘1’ && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
if wback && registers == ‘1’ then UNPREDICTABLE;
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
LDM {!},
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 0 0 0 1 0 W 1 Rn register_list
if W == ‘1’ && Rn == ‘1101’ && BitCount(register_list) >= 2 then SEE POP;
n = UInt(Rn); registers = register_list; wback = (W == ‘1’);
if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
if wback && registers == ‘1’ && ArchVersion() >= 7 then UNPREDICTABLE;
Assembler syntax
LDM {!},
where:
See Standard assembler syntax fields on page A8-7.
A8-110 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B