ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
C10.3.2 Watchpoint Fault Address Register (DBGWFAR)
The Watchpoint Fault Address Register, DBGWFAR, returns information about the address of the
instruction that accessed a watchpointed address.
The DBGWFAR:
is debug register 6 at offset 0x018
is a read/write register
is implemented differently in different versions of the Debug architecture:
v6 Debug In v6 Debug, the DBGWFAR can be accessed only through CP15.
v6.1 Debug
In v6.1 Debug, the DBGWFAR can be accessed through the debug register interfaces,
and using the CP15 access is deprecated.
v7 Debug In v7 Debug, the CP15 encoding used for the DBGWFAR in v6 Debug is UNDEFINED in
User mode and UNPREDICTABLE in privileged modes. The DBGWFAR can be accessed
only through the debug register interfaces.
The format of the DBGWFAR is:
31 0
(Instruction address) + offset
(Instruction address) + offset, bits [31:0]
When Watchpoint debug events are permitted, on every Watchpoint debug event the
DBGWFAR is updated with the address of the instruction that accessed the watchpointed
address plus an offset that depends on the processor instruction set state when the instruction
was executed:
8 if the processor was in ARM state
4 if the processor was in Thumb or ThumbEE state
an IMPLEMENTATION DEFINED offset if the processor was in Jazelle state.
See Memory addresses on page C3-23 for a definition of the Instruction Virtual Address
(IVA) used to update the DBGWFAR.
The debug logic reset value of the DBGWFAR is UNKNOWN.
A processor with a trivial implementation of the Jazelle extension can implement DBGWFAR[0] as
RAZ/WI, see Trivial implementation of the Jazelle extension on page B1-81 for more information. In such
an implementation, software must use a SBZP policy when writing to DBGWFAR[0].
C10-28 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B