ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
B1.6.10 Reset
Using WFI to indicate an idle state on bus interfaces
A common implementation practice is to complete any entry into power-down routines with a WFI
instruction. Typically, the WFI instruction:
1. forces the suspension of execution, and of all associated bus activity
2. ceases to execute instructions from processor.
The control logic required to do this typically tracks the activity of the bus interfaces of the processor. This
means it can signal to an external power controller that there is no ongoing bus activity.
The exact nature of this interface is IMPLEMENTATION DEFINED, but the use of Wait For Interrupt as the only
architecturally-defined mechanism that completely suspends execution makes it very suitable as the
preferred power-down entry mechanism for future implementations.
Pseudocode details of Wait For Interrupt
The WaitForInterrupt() pseudocode procedure optionally suspends execution until a WFI wake-up event or
reset occurs, or until some earlier time if the implementation chooses.
On an ARM processor, when the Reset input is asserted the processor immediately stops execution of the
current instruction. When Reset is de-asserted, the actions described in Exception entry on page B1-34 are
performed, for the Reset exception. The processor then starts executing code, in Supervisor mode with
interrupts disabled. Execution starts from the normal or high reset vector address, 0x00000000 or 0xFFFF0000,
as determined by the reset value of the SCTLR.V bit. This reset value can be determined by an
IMPLEMENTATION DEFINED configuration input signal.
Note
The ARM architecture does not distinguish between multiple levels of reset. A system can provide
multiple distinct levels of reset that reset different parts of the system. These all correspond to this
single reset exception.
The reset value of the SCTLR.EE bit can be defined by a configuration input signal. If this is done,
that value also applies to the CPSR.E bit on reset. For more information see:
— c1, System Control Register (SCTLR) on page B3-96 for a VMSA implementation
— c1, System Control Register (SCTLR) on page B4-45 for a PMSA implementation.
The following pseudocode describes how this exception is taken:
// TakeReset()
// ===========
TakeReset()
// Enter Supervisor mode and (if relevant) Secure state, and reset CP15. This affects
// the banked versions and values of various registers accessed later in the code.
// Also reset other system components.
CPSR.M = ‘10011’; // Supervisor mode
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