ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Exceptions
In Monitor debug-mode the behavior on the exception generated as a result of a Breakpoint, BKPT
Instruction, or Vector Catch debug events is as follows:
the IFSR is updated with the encoding for a debug event, IFSR[10,3:0] = 0b00010
the IFAR is UNKNOWN following these debug exceptions
the DFSR, DFAR and DBGWFAR are unchanged.
In Monitor debug-mode the behavior on the exception generated as a result of a Watchpoint debug event is
as follows:
the IFSR and IFAR are unchanged.
the DFSR is updated with the encoding for a debug event, DFSR[10,3:0] = 0b00010.
the Domain and Write fields in the DFSR, DFSR[11,7:4], are UNKNOWN. However, an ARMv6
watchpoint sets the Domain field.
the DFAR is UNKNOWN.
the DBGWFAR is updated with the Instruction Virtual Address (IVA) of the instruction that accessed
the watchpointed address, plus an offset that depends on the instruction set state of the processor for
that instruction:
— 8 in ARM state
— 4 in Thumb and ThumbEE states
— IMPLEMENTATION DEFINED in Jazelle state.
See Memory addresses on page C3-23 for a definition of the IVA used to update the DBGWFAR.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C4-5