ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
0b0001 Supported Level 1 Harvard cache line maintenance operations by MVA are:
Clean data cache line by MVA
Invalidate data cache line by MVA
Clean and invalidate data cache line by MVA
Clean instruction cache line by MVA.
0b0010 As for 0b0001, and adds:
Invalidate branch predictor by MVA, if branch predictor is implemented.
If this field is set to a value other than 0b0000 then the L1 unified cache VA field, bits [7:4],
must be set to 0b0000.
c0, Memory Model Feature Register 2 (ID_MMFR2)
The format of the ID_MMFR2 is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
HW
access flag
WFI
stall
HW access flag, bits [31:28]
Mem
barrier
Unified
TLB
Harvard
TLB
L1 Harvard
range
L1 Harvard
bg prefetch
Indicates support for a Hardware access flag, as part of the VMSAv7 implementation.
Permitted values are:
0b0000 Not supported.
0b0001 Support for VMSAv7 access flag, updated in hardware.
On an ARMv7-R implementation this field must be 0b0000.
WFI stall, bits [27:24]
Indicates the support for Wait For Interrupt (WFI) stalling. Permitted values are:
0b0000 Not supported.
0b0001 Support for WFI stalling.
L1 Harvard
fg prefetch
Mem barrier, bits [23:20]
Indicates the supported CP15 memory barrier operations:
0b0000 None supported.
0b0001 Supported CP15 Memory barrier operations are:
Data Synchronization Barrier (DSB). In previous versions of the ARM
architecture, DSB was named Data Write Barrier (DWB).
0b0010 As for 0b0001, and adds:
Instruction Synchronization Barrier (ISB). In previous versions of the
ARM architecture, the ISB operation was called Prefetch Flush.
Data Memory Barrier (DMB).
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