ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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<strong>ARM</strong> Instruction Set Encoding<br />

A5.7 Unconditional instructions<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 op1 Rn op<br />

Table A5-23 shows the allocation of encodings in this space.<br />

Other encodings in this space are UNDEFINED in <strong>ARM</strong>v5 <strong>and</strong> above.<br />

All encodings in this space are UNPREDICTABLE in <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v4T.<br />

Table A5-23 Unconditional instructions<br />

op1 op Rn Instruction See Variant<br />

0xxxxxxx - - - Miscellaneous instructions, memory hints, <strong>and</strong><br />

Advanced SIMD instructions on page A5-31<br />

100xx1x0 - - Store Return State SRS on page B6-20 v6<br />

100xx0x1 - - Return From Exception RFE on page B6-16 v6<br />

101xxxxx - - Branch with Link <strong>and</strong> Exchange BL, BLX (immediate) on<br />

page A8-58<br />

11000x11 - not 1111 Load Coprocessor (immediate) LDC, LDC2 (immediate) on<br />

page A8-106<br />

11001xx1 - 1111 Load Coprocessor (literal) LDC, LDC2 (literal) on<br />

page A8-108<br />

1101xxx1 - 1111<br />

11000x10<br />

11001xx0<br />

1101xxx0<br />

- - Store Coprocessor STC, STC2 on page A8-372 v5<br />

11000100 - - Move to Coprocessor from two<br />

<strong>ARM</strong> core registers<br />

11000101 - - Move to two <strong>ARM</strong> core registers<br />

from Coprocessor<br />

A5-30 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B<br />

v5<br />

v5<br />

v5<br />

MCRR, MCRR2 on page A8-188 v6<br />

MRRC, MRRC2 on page A8-204 v6<br />

1110xxxx 0 - Coprocessor data operations CDP, CDP2 on page A8-68 v5<br />

1110xxx0 1 - Move to Coprocessor from<br />

<strong>ARM</strong> core register<br />

1110xxx1 1 - Move to <strong>ARM</strong> core register from<br />

Coprocessor<br />

MCR, MCR2 on page A8-186 v5<br />

MRC, MRC2 on page A8-202 v5

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