ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Block transfer operations
ARMv6 Differences
ARMv7 does not support CP15 register block transfer operations, and they are optional in ARMv6.
Table G-8 summarizes block transfer operations. Permitted combinations of the block transfer operations
are:
all four operations
clean, clean and invalidate, and invalidate operations
none of the operations.
If an operation is not implemented, then it must cause an Undefined Instruction exception.
Operation
Blocking a or
non-blocking
Instruction or
data
a. See Blocking and non-blocking behavior on page AppxG-42
Table G-8 Block transfer operations
User or
privileged
Prefetch range Non-blocking Instruction or data User or privileged None
Exception
Behavior
Clean range Blocking Data only User or privileged Data Abort
Clean and Invalidate range Blocking Data only Privileged Data Abort
Invalidate range Blocking Instruction or data Privileged Data Abort
An MCRR instruction starts each of the range operations. The data of the two registers specifies the Block start
address and the Block end address. All block operations are performed on the cachelines that include the
range of addresses between the Block start address and Block end address inclusive. If the Block start
address is greater than the Block end address the effect is UNPREDICTABLE.
ARMv6 supports only one block transfer at a time. Attempting to start a second block transfer while a block
transfer is in progress causes the first block transfer to be abandoned and starts the second block transfer.
The Block Transfer Status Register indicates whether a block transfer is in progress. The register can be
polled before starting a block transfer, to ensure any previous block transfer operation has completed.
All block transfers are interruptible. When blocking transfers are interrupted, the LR value that is captured
is (address of instruction that launched the block operation + 4). This enables the standard return mechanism
for interrupts to restart the operation.
For performance reasons, ARM recommends that implementations permit the following instructions to be
executed while a non-blocking prefetch range instruction is being executed. In such an implementation, the
LR value captured on an interrupt is determined by the instruction set state presented to the interrupt in the
following instruction stream. However, implementations that treat a prefetch range instruction as a blocking
operation must capture the LR value as described in the previous paragraph.
If the FCSE PID is changed while a prefetch range operation is running, it is UNPREDICTABLE at which point
this change is seen by the prefetch range. For information about changing the FCSE PID see c13, FCSE
Process ID Register (FCSEIDR) on page B3-152.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-41