ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
Z, bit [11] Branch prediction enable bit. This bit is used to enable branch prediction, also called
program flow prediction:
0 program flow prediction disabled
1 program flow prediction enabled.
If program flow prediction cannot be disabled, this bit is RAO/WI. Program flow prediction
includes all possible forms of speculative change of instruction stream prediction. Examples
include static prediction, dynamic prediction, and return stacks.
If the implementation does not support program flow prediction this bit is RAZ/WI.
F (bit [10]) The meaning of this bit is IMPLEMENTATION DEFINED.
R (bit [9]) ROM protection bit, supported for backwards compatibility. The effect of this bit is
described in Table H-6 on page AppxH-23. Use of this feature is deprecated in ARMv6 and
the feature is not supported in ARMv7.
S (bit [8]) System protection bit, supported for backwards compatibility. The effect of this bit is
described in Table H-6 on page AppxH-23. Use of this feature is deprecated in ARMv6 and
the feature is not supported in ARMv7.
B (bit [7]) This bit configures the ARM processor to the endianness of the memory system:
0 Little-endian memory system (LE)
1 Big-endian memory system (BE-32).
ARM processors that support both little-endian and big-endian memory systems use this bit
to configure the ARM processor to rename the four byte addresses in a 32-bit word.
Endian support changed in ARMv6. Use of this feature is deprecated in ARMv6 and the
feature is not supported in ARMv7.
An implementation can include a configuration input signal that determines the reset value
of the B bit. If there is no configuration input signal to determine the reset value of this bit
then it resets to 0.
Bits [6:4] RAO/SBOP.
W (bit [3]) This is the enable bit for the write buffer:
0 Write buffer disabled
1 Write buffer enabled.
If the write buffer is not implemented, this bit is RAZ/WI. If the write buffer cannot be
disabled, this bit is RAO and ignores writes. Use of this feature is deprecated in ARMv6 and
the feature is not supported in ARMv7
C, bit [2] Cache enable bit. This is a global enable bit for data and unified caches:
0 Data and unified caches disabled
1 Data and unified caches enabled.
If the system does not implement any data or unified caches that can be accessed by the
processor at any level of the memory hierarchy, this bit is RAZ/WI.
AppxH-40 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B