ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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<strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 Differences<br />

H.1 Introduction to <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5<br />

H.1.1 Debug<br />

<strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 defined the instruction set support <strong>and</strong> the programmers’ model that applies to the<br />

general-purpose registers <strong>and</strong> the associated exception model. These architecture versions are fully<br />

described in the <strong>ARM</strong> <strong>Architecture</strong> <strong>Reference</strong> <strong>Manual</strong> (DDI 0100).<br />

Note<br />

This appendix is a summary of the <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 architecture variants. It is expected that the majority<br />

of requirements for architecture information on <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 are satisfied by this appendix <strong>and</strong> the<br />

rest of this manual. However the <strong>ARM</strong> <strong>Architecture</strong> <strong>Reference</strong> <strong>Manual</strong> (DDI 0100) might be required for<br />

more information specific to <strong>ARM</strong>v4 or <strong>ARM</strong>v5.<br />

Memory support is IMPLEMENTATION DEFINED in <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5. In practice, use of CP15 to support<br />

the Virtual Memory System <strong>Architecture</strong> (VMSA) or Protected Memory System <strong>Architecture</strong> (PMSA) is<br />

st<strong>and</strong>ard in <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 implementations, but this is not an architectural requirement. For this<br />

reason, the datasheet or Technical <strong>Reference</strong> <strong>Manual</strong> for a particular <strong>ARM</strong> processor is the definitive source<br />

for its memory <strong>and</strong> system control facilities. This appendix does not specify absolute requirements on the<br />

functionality of CP15 or other memory system components. Instead, it contains guidelines designed to<br />

maximize compatibility with current <strong>and</strong> future <strong>ARM</strong> software.<br />

This appendix concentrates on the features supported in <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5, highlighting:<br />

features common across all architecture variants<br />

features supported for legacy reasons in <strong>ARM</strong>v6, but not in <strong>ARM</strong>v7<br />

features unique to the <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 variants.<br />

Debug is not architecturally-defined in <strong>ARM</strong>v4 or <strong>ARM</strong>v5. <strong>ARM</strong> implementations have traditionally<br />

supported halting debug through a JTAG port. While the support of debug features is similar across <strong>ARM</strong><br />

implementations, the timing <strong>and</strong> control sequencing required for access varies. Debug support in <strong>ARM</strong>v4<br />

<strong>and</strong> <strong>ARM</strong>v5 is microarchitecture dependent <strong>and</strong> so in architectural terms is IMPLEMENTATION DEFINED.<br />

H.1.2 <strong>ARM</strong>v6 <strong>and</strong> <strong>ARM</strong>v7<br />

The <strong>ARM</strong> architecture was extended considerably in <strong>ARM</strong>v6. This means that a large proportion of this<br />

manual does not apply to earlier architecture variants <strong>and</strong> can be ignored with respect to <strong>ARM</strong>v4 <strong>and</strong><br />

<strong>ARM</strong>v5.<br />

The key changes in <strong>ARM</strong>v6:<br />

add:<br />

— the <strong>ARM</strong> SIMD instructions to improve execution of multimedia <strong>and</strong> other DSP applications<br />

— instructions for improved context switching.<br />

AppxH-2 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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